在可穿戴式設(shè)計中選擇外圍設(shè)備和集成存儲器

　　新一代可穿戴技術(shù)正在啟用高度集成的片上系統(tǒng)（SoC）設(shè)計。最新的32位微控制器核心從ARM和MIPS提供高性能的支持，如Android Wear新的操作系統(tǒng)，并加入了廣泛的外設(shè)，以支持新的顯示器，交互式接口和傳感器應(yīng)用。

　　移動到32位內(nèi)核允許高級開發(fā)工具不僅用于用戶應(yīng)用程序，還用于整個設(shè)計的管理，特別是外圍設(shè)備的電源管理。能夠?qū)崿F(xiàn)復(fù)雜的算法，以優(yōu)化功耗是至關(guān)重要的，以獲得最佳的電池壽命，這是緊密耦合的外設(shè)在系統(tǒng)芯片上實現(xiàn)的可穿戴式設(shè)計設(shè)備。

　　The choice of the processor core architecture is often down to the experience of the system architect and the design team， as well as strategic corporate relationships. There are many designers adept at developing on both the ARM and MIPS platforms， using high level C development tools and the peripheral management tools that come with each of the different silicon suppliers.

　　Devices such as Silicon Labs‘ Tiny Gecko EFM32TG842 with a central ARM Cortex-M3 processor core （shown in Figure 1） are aimed directly at wearable designs with a small size and low power consumption but also a range of peripherals optimized for such applications. Freescale Semiconductor also has a range of system-on-chip devices based on the ARM Cortex-M0+ devices in its KL16 family that are part of its WaRP wearable development platform.